Monday, March 08, 2010

W5300 High Performance Hardwired TCP/IP PHY Embedded Chip

W5300 (Fully Hardwired Network protocol Embedded Ethernet Controller designed for high speed required embedded system)

Performance Benefits High Speed Data Communication : Over 50Mbps at application Layer More Stable Data Communication
Implementation Benefits Easy & Simple control like memory Save developing time and area
Cost Benefits MAC & PHY embedded into W5300
Development Benefits Easy implemented not only at the OS but also non-OS enviroment

- Supports hardwired TCP/IP protocols : TCP,UDP, ICMP, IPv4, ARP, IGMPv2, PPPoE, Ethernet
- Supports 8 independent SOCKETs simultaneously
- High network performance : Up to 80Mbps (DMA)
- Supports hybrid TCP/IP stack(software and hardware TCP/IP stack)
- IP Fragmentation is not supported
- Internal 128Kbytes memory for data communication(Internal TX/RX memory)
- More flexible allocation internal TX/RX memory according to application throughput
- Supports memory-to-memory DMA (only 16bit Data bus width & slave mode)
- Embedded 10BaseT/100BaseTX Ethernet PHY
- Supports auto negotiation (Full-duplex and half duplex)
- Supports auto MDI/MDIX(Crossover)
- Supports network Indicator LEDs (TX, RX, Full/Half duplex, Collision, Link, Speed)
- Supports a external PHY instead of the internal PHY
- Supports 16/8 bit data bus width
- Supports 2 host interface mode(Direct address mode & Indirect address mode)
- External 25MHz operation frequency (For internal PLL logic, period=40ns)
- Internal 150MHz core operation frequency (PLL_CLK, period=about 6.67ns)
- Network operation frequency (NIC_CLK : 25MHz(100BaseTX) or 2.5MHz(10BaseT))
- 3.3V operation with 5V I/O signal tolerance
- Embedded power regulator for 1.8V core operation
- 0.18 ┬Ám CMOS technology
- 100LQFP 14X14 Lead-Free Package