Wednesday, December 09, 2009

W3150A vs. W3150A+

WIZnet Chip (Fully Hardwired TCP/IP stack)

Performance Benefits Line-Speed Data transmission by hardwired logic
Implementation Benefits Easy control way like memory
Cost Benefits
No OS required
Application Benefits - As an Internet Controller : Easy embedded to controllers or data collectors with low-end MCUs
-As an Internet Accelerator : Reducing Jitter with fixed processing time by hardware. Enhancing video and voice quality.
- Support Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IGMP, IPv4, ARP, PPPoE, Ethernet
- Support ADSL connection (with support PPPoE Protocol with PAP/CHAP Authentication mode)
- Supports 4 independent sockets simultaneously
- Not support IP Fragmentation
- Standard MII Interface for Ethernet-PHY chip
- Supports 10BaseT/100BaseTX
- Supports full-duplex mode
- Internal 16Kbytes Memory for Tx/Rx Buffers
- 0.18 µm CMOS technology
- 3.3V operation with 5V I/O signal tolerance
- Small 64 Pin LQFP Package
- Lead-Free Package

Block Diagram
Difference between W3150A and W3150A+

W3150A+ W3150A
Three MCU interface
(Direct, Indirect and SPI)
Only two interface possible
(Direct & Indirect)
Pin no.33 used for SPI enable Pin no.33 used for PCLOCK
Interrupt Register clear by writing on particular bit Interrupt Register clear by
reading the register
Add "Send_OK" interrupt is added
when send operation is complete
No interrrupt when send operation is complete
No delayed ACK mode supported in TCP Not possible
UDP zero checksum is removed in TX UDP zero checksum is there in
TX and RX both